1. Technical Field
The present invention relates to methods of fabricating semiconductor devices and, more specifically, to methods of fabricating a semiconductor device including a fin field effect transistor (Fin-FET).
2. Description of the Related Art
A conventional field effect transistor (FET) includes an active region, a gate electrode crossing over the active region, and source/drain electrodes formed in active regions adjacent to opposite sides of the gate electrode. An active region below the gate electrode is used as a channel region (through which charges migrate). That is, the channel region refers to an active region between the source electrode and the drain electrode.
With the recent trend toward higher integration density of semiconductor devices, the width of gate electrodes and the width of active regions are decreasing. However, in the case of the FET structure, if the width of a gate electrode decreases, the length of a channel region (i.e., a space between a source region and a drain region) also decreases. As a result, a short channel effect (SCE) such as drain induced barrier lowering (DIBL) or punch-through may occur. Further, if the width of an active region decreases, the width of a channel also decreases causing a narrow width effect such as drain current lowering.
Essentially, the short channel effect results from incomplete control of the gate electrode for an electronic state of the channel region. In view of the foregoing, fin field effect transistors (Fin-FETs), each having a vertical channel region, have been proposed in recent years. In such a Fin-FET, a gate electrode controls a channel region from three sides to be more effective in suppressing the short channel effect. Moreover, the width of the channel increases due to a vertical channel region (i.e., a sidewall of a fin) so as to be more effective in suppressing the narrow channel effect than conventional planar FETs. Nevertheless, since most memory transistors detect information stored in a memory cell by means of a method for sensing drain current, FET structures with increased drain current have been required to enhance a sensing characteristic of a memory cell.